طراحي مدار محاسباتي تقريبي پايه در معماري‌هاي متداول و پردازش در حافظه مبتني بر فناوري‌هاي سي‌ماس و ممريستور

The power and memory walls are among the most important factors limiting the growth of processorsʹ efficiency. Securing energy resources required by the processing units and the environmental challenges of fossil fuel consumption have also become essential concerns for designers. Applying approximate computing in error-resilient data-intensive processing applications is eva‎luated as an efficient method to overcome the power wall. In this computational method, along with reducing the hardware complexity, the computational accuracy is also reduced to a limited extent. In-memory Computing (IMC) is one of the solutions to overcome the memory wall, and it is considered a substitute for Von-Neumann architecture. A memristor is an electrical element manufactured in the semiconductor industry and has been accompanied by ever-increasing progress in energy consumption, endurance, and writing time. This electrical device is one of the emerging technologies that can be applied as both a memory cell and processing element in IMC. Various design methods, such as Material Implication (IMPLY) logic, have been introduced to implement memristive arithmetic circuits. IMPLY logic is one of the flexible and reliable design methods compatible with the structure of memristive crossbar arrays. This dissertation introduced a method to design IMPLY-based serial approximate full adders with inexact Sum and Carry out (Cout), and the limitation of the Error Distance (ED) is considered. This method is proposed to reduce the number of computational steps and the energy consumption required for basic arithmetic structures. The output of this design method is six different serial approximate full adders. An IMPLY-based serial approximate full adder cell was also proposed to prevent the propagation of false Cout bit. The main goal is truncating error propagation from the Least Significant Bits (LSBs) to the approximate adders and other basic approximate arithmetic circuitsʹ Most Significant Bits (MSBs). The proposed circuits have improved the number of computational steps and energy consumption compared to the exact circuit by 45%-73% and 46%-73%, respectively, and by a maximum of 14% and 21% compared to the approximate serial circuit, respectively. The computational accuracy of the proposed circuits has been ensured by examining the error and image quality eva‎luation criteria in different processing applications. Establishing a suitable compromise between computational accuracy and improving circuit eva‎luation criteria was also investigated by examining three valid Figures of Merit (FoM) consisting of circuit eva‎luation criteria such as energy consumption and error analysis metrics such as error distance.

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