چكيده لاتين
Today, electronic components have become an inseparable part of human life, storing sensitive and confidential information. The use of these components in critical and sensitive circuits of airplanes, large factory infrastructures, medical equipment, military and defense tools, etc., has intensified their security risks, as they can sometimes lead to irreparable damages. There are two main challenges for hardware security specialists in this regard. One is the existence of hardware security vulnerabilities due to outsourcing the manufacturing of electronic components for quick and cheap supply, which creates numerous security risks such as theft of the circuitʹs intellectual property core, unauthorized fabrication and duplication, hardware misuse and manipulation, and ultimately the insertion of hardware trojans. The other challenge is the reduction in size and delay of electronic components based on integrated circuit technology, which confronts them with a shortage of hardware space and delay limitations. of course, various solutions for hardware security have been proposed, with hardware obfuscation—by complicating reverse engineering and reducing an attackerʹs access to the original netlist—being particularly emphasized. In hardware obfuscation, by adding additional logic to the circuit, its original netlist (structure and function) becomes obscure to an attacker. The logic locking technique, which is one of the obfuscation methods, prevents an attacker from accessing the original netlist by inserting key gates into it and hiding the circuitʹs function and structure. The circuit only operates correctly when the correct key is applied; otherwise, it remains in an ambiguous state. Solutions proposed in recent years for obfuscating integrated circuits have high hardware overhead and significant delay, while attacks are also evolving alongside security techniques. Therefore, it is essential to establish a balance between hardware overhead and resistance to attacks. In other words, in addition to increasing the level of hardware security, it is necessary to reduce overhead in terms of space consumption and delay. In this research, considering hardware challenges such as limited space consumption, delay constraints, unauthorized use and duplication, and insertion of hardware trojans, a solution has been proposed to enhance security for all components of integrated circuits. This solution includes core IP security and prevention of hardware trojan insertion in the gate-level netlist and finite state machine. It is worth mentioning that in the proposed method, both hardware overhead is reduced and acceptable resistance against notable attacks such as SAT attacks is provided. To achieve this, an optimal number of key gates and ambiguous states have been added to reduce space consumption and delay overhead.For core IP security and preventing unauthorized use and duplication, a watermarking method based on cryptography using elliptic curve algorithms has been employed. By designing an adder circuit and using data encoding, speed has been reduced by approximately 13% and space consumption by about 15%. Additionally, to prevent hardware trojan insertion in the gate-level netlist of the circuit, low-testability signals have been locked using an interleaved insertion method along paths with the highest branching. The proposed solution not only provides acceptable resistance against SAT attacks but also reduces hardware overhead by about 5% and delay by around 4%. Finally, using state machine obfuscation methods, the number of states and transitions in the circuit becomes obscure to an attacker. The proposed solution offers a higher level of security compared to similar methods while achieving approximately 7% lower hardware overhead and about 4% less delay than similar approaches. While providing an acceptable level of resistance against attacks, it also reduces space consumption and delay.
