طراحي يك سلول تمام جمع‌كننده‌ مبتني بر فناوري 32 نانومتر نانولوله‌هاي كربني با تكنيك ورودي انتشار گيت

The limitations caused by the scaling in the common technology of silicon transistors (CMOS) have led researchers to find a suitable replacement for this technology. Meanwhile, carbon nanotube field-effect transistors (CNFETs) have been proposed as the main alternative for replacement due to their characteristics and similarities with conventional CMOS technology. For this reason, the design and construction of gates and basic circuits in CNFET technology for use in larger hardware has become one of the important research topics in this field. In the meantime, the design of all adders, which are considered as the basis of other arithmetic operations, and improving their performance leads to improving the performance of larger circuits, has gained special importance. In the current research, a full collector using carbon nanotube field effect transistor technology has been introduced, which has been tried to perform better than previous designs in terms of power consumption parameter. The results showed that all the proposed adder has improved the power consumption between 6% and 61%, and also this design has improved the delay and PDP parameters by 9% to 69% and 1% to 8%, respectively, compared to a number of previous works. . For a more accurate eva‎luation of the designed design, larger adder circuits including wave-like adders and fast adders such as digit selection adders and digit jump adders were also designed and analyzed using all the proposed adders. So that the waveform adder designed with all these adders has 41% improvement in delay. The improvement of the design of the digit selection adder using all the proposed adders for the delay and PDP parameters is 93% and 93%, respectively, and the digit jump adder made with this all adder compared to the digit jump adder made with all previous adders, 48% of In terms of power, 37% in terms of delay and 39% in terms of PDP have improved. All the simulations in this research have been done using HSPICE software, and the results of the simulation at different voltages, temperatures and with different capacitor loads show that all the proposed collector has provided a significant improvement in power compared to the previous designs and has a delay and PDP that can be used. It is accepted.

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