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RecordNumber
2298
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Author
Bellido, Manuel J.,1964-
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Title
Logic-timing simulation and the degradation delay model
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Author Statement
Manuel J. Bellido, Jorge Juan, Manuel Valencia.
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Publication
Imperial College Press
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Publication Year
c2006
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Collation
xvii, 267 p. ill.
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Notes
Includes bibliographical references
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Subject
Timing circuits. , Integrated circuits , Metal oxide semiconductors, Complementary.
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ADDED ENTRIES
Juan Chico, Jorge. , Valencia, Manuel.
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Main class
003
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Sub class
.3
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Cutter no
B4171l
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ISBN
1860945899
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Link To Document :
