RecordNumber
2298
Author
Bellido, Manuel J.,1964-
Title
Logic-timing simulation and the degradation delay model
Author Statement
Manuel J. Bellido, Jorge Juan, Manuel Valencia.
Publication
Imperial College Press
Publication Year
c2006
Collation
xvii, 267 p. ill.
Notes
Includes bibliographical references
Subject
Timing circuits. , Integrated circuits , Metal oxide semiconductors, Complementary.
ADDED ENTRIES
Juan Chico, Jorge. , Valencia, Manuel.
Main class
003
Sub class
.3
Cutter no
B4171l
ISBN
1860945899